Tessera aims to wrap up IPO
Published: 30 Oct 2003 15:45 GMT
To tackle these problems, packaging experts constructed large, fairly rigid packages that could reduce localised flexing and accommodate numerous leads. This, however, created other problems. Large packages mean longer electrical leads, which mean greater delays in getting signals to and from the chip. Large packages are also, by definition, large, which chafes against manufacturers' desires to shrink their products.
Tessera went the opposite way with what it called chip scale packaging. In chip scale packaging, a semiconductor rests on a flexible substrate and the bundle is then wrapped in polyimide tape, Tobak said. Aluminum traces inside the substrate connect the chip to metallic balls on the outside surface of the tape. (Chip scale package refers to the general concept -- the actual packages are sold under names like the micro Ball Grid Array, or BGA, package.)
As a result, chip scale packages are small -- about the same size as the chip -- and they bend to accommodate the different flexing characteristics of the board and the chip.
Additionally, Tessera put the chip face down. This reduces the length of electrical connections between the chip's transistors (located on the upper surface of the chip) and the motherboard, thereby improving performance. In traditional "face up" packages, wires sprout from the top of the chip and coil down.
The size and the nature of these packages allowed for another possibility: multi-chip packaging. Chips get tested after packaging. Multi-chip packages, therefore, have historically been risky because one bad part can spoil the whole bundle.
"The holy grail in packaging has been to come up with multi-chip modules. Everyone has tried it and failed," Tobak said.
With chip scale packaging, each chip can be tested individually and then tiled together in a multi-chip package.
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