Five years ago: Grove details new Intel DIB architecture
Published: 14 May 2002 07:01 BST
First published May 14, 1997.
Intel finally went public on the radical new architecture required by the Pentium II processor last week. Banging the drum for the Dual Independent Bus (DIB) architecture, CEO Andy Grove said that other architectures being pursued by rivals are bandwidth equivalents of "valleys of death".
DIB is demanded by the Pentium II (to be formally announced early in May) and comprises both an L2 cache bus and processor-to-memory system bus. The single dedicated L2 cache on the Pentium II processor is twice as fast as the L2 cache on a Pentium processor, according to Intel. The system bus is pipelined and allows simultaneous transactions. In all, DIB leads to three times the bandwidth of a single bus architecture, Intel claims. The chip maker also says a 100MHz bus version is in the works. The Pentium II processor and the DIB are accommodated in a new Single Edge Contact (SEC) cartridge which fits into a new interface called Slot 1.
In a speech to IT managers at Compaq's "Innovate" conference last week, Grove said DIB will accelerate the speed the processor exchanges data with the memory and graphics subsystems, and added the speed increases will be scalable with processor performance.
"Processor performance alone is not enough," Grove said. "We must address two 'valleys of death,' namely, the processor-to-memory and processor-to-graphics bus bandwidth bottlenecks." DIB, in tandem with a new graphics bus architecture called Accelerated Graphics Port (AGP) to be introduced late in 1997, is Intel's answer to the problem.
Later in his address, Grove demonstrated 300MHz and 500MHz Pentium II systems in 3D graphics modelling routines, and a 266MHz Pentium II system running native Java applications.
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