Intel server revamp mirrors AMD's approach
Published: 11 Sep 2006 15:10 BST
…to communicate directly with memory. That's because one processor can quickly retrieve data stored in memory connected to another chip.
"The biggest advantage CSI offers is performance and the fact that you basically get a direct connection between the processors. That results in reduced latency between the processors," said Craig Church, Unisys's director of server development. The integrated memory controllers, too, will reduce latency, or communication delays, when a chip is fetching data from its own memory, he added.
AMD has adopted the integrated memory controller in all its x86 chips, but it's not alone in endorsing the approach. IBM's Power and Sun's UltraSparc, which compete with Intel's server line, have had integrated memory controllers for years.
With a chipset controlling memory instead of the main processor, "You basically have this middleman, and that introduces a significant amount of latency in the memory transaction," said Mercury Research analyst Dean McCarron.
An integrated memory controller not only lets main memory respond faster, it also allows cache sizes, and therefore chip-manufacturing expenses, to be reduced. Indeed, smaller cache sizes have helped AMD remain competitive with Intel, even though it's about a year behind in its transition to more advanced manufacturing with smaller circuitry elements.
Intel defends its decision to stick with the front-side bus as long as it has, arguing that the choice has given it flexibility in memory standards and that it's been able to compensate elsewhere to keep up with performance.
"Our competition had to go to an integrated memory controller because they can't get the same... amount of cache on a die as we can," Kilroy said. "And we've been able to scale the front-side bus far greater than ever thought. We're now at 1333MHz. The speculation was that we wouldn't be able to scale to that."
Lowering design barriers
CSI is designed to lower hardware barriers, making it less expensive for server makers to design servers using both chips. Indeed, the word "common" refers to the fact that Itanium and Xeon use the interface.
With CSI, a server could be designed to be totally "plug-compatible," meaning the chips would be interchangeable, Church said. "From a Unisys perspective, if a customer wants an Itanium system, we take an Itanium processor and plug it into our common platform. If they want Xeon, we plug a Xeon into our common platform," he said. "That essentially is the nirvana, and it is the goal."
Nevertheless, server makers are faced with some differences in CSI for Xeon and Itanium, Marcello said. "The CSI implementations are 95 percent the same, but there's a little bit of difference there. For that reason, we'll be close but not exactly the same," he said. However, they will be similar enough that some joint design work can be shared, he added.
Keeping up with the Joneses
Once Intel matches AMD's chip communication technologies, it will become a better competitor, Brookwood said.
"The big issue for Intel is moving from the front-side bus architecture to more of a distributed architecture," Brookwood said. "Once they get that in place and have workable schemes for managing cache coherency and memory access across processors, then they will be well-positioned to compete on almost any basis with what AMD has been doing. The Direct Connect architecture has been AMD's not-so-secret sauce for the last four years."
But AMD has plans of its own. In 2007, it will move to HyperTransport 3.0. The update increases communication speeds and enables construction of 16-processor servers instead of the eight-processor machines that HyperTransport currently permits, said Marty Seyer, a vice president in AMD's commercial business unit.
In addition, the company believes the openness of HyperTransport is an advantage. The technology is governed and licensed by the HyperTransport Consortium.
One company very interested in HyperTransport's openness is Cray. "It's a huge benefit," said Jan Silverman, senior vice president of corporate strategy at the supercomputer maker. "It's not free, but the terms are much more palatable than anything that I have seen from Intel in the past."
The openness also means Cray can use HyperTransport to connect Opteron chips to its own networking chips. And when it wants to use HyperTransport to plug calculation acceleration engines into a computer, it can buy them from a company called DRC Computer that specializes in the engines, instead of having to make its own.
AMD's Opteron years have left an impression on Silverman that Intel will have to work hard to reverse. "There was a point in time when Intel used to lead the industry. Now they're following AMD on 64 bits, following on dual-core, following on low-power consumption chips, and now they're going to follow AMD in exposing their Intel architecture," Silverman said.
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