Sparc goes open source
Published: 21 Mar 2006 09:25 GMT
Sun on Tuesday plans to release the underlying design of its UltraSparc T1 Niagara processor under the terms of the GPL.
The move fulfils a commitment to employ the open source licence that Sun's president, Jonathan Schwartz, made at the Open Source Business Conference in January. David Yen, executive vice president of Sun's Sparc server group, is expected to discuss the move at the Multi-Core Expo in Santa Clara, California, where Sun also has its headquarters.
Sun's UltraSparc T1 has eight cores, each able to run four threads. When one thread stalls because it has to retrieve data from comparatively slow memory, a core switches to another thread. This approach is designed to let the T2000 and forthcoming T1000 servers run many jobs in parallel with good performance, even though an individual job may not get done as fast as on a more single-minded chip.
The OpenSparc project is designed to increase the relevance of Sun's Sparc family, which has lost market share in recent years to IBM's Power and to x86 chips from Intel and AMD. The company hopes that making the designs available in the Verilog format will trigger research projects and commercial developments.
The GPL was developed by Richard Stallman and is a cornerstone of the free software movement and the closely related open source software concept. It lets a program's underlying source code be seen, modified and distributed by anyone, so long as anyone who distributes a changed version publishes those changes under the same licence.
One company, SimplyRISC, plans to make a single-core version of Niagara for embedded computing devices, which often require low power consumption. And a chip design company called Aldec plans to make its Riviera software available for 90-day free trials so people can simulate Verilog designs.
In conjunction with the chip designs, Sun also published at OpenSparc.net UltraSparc architecture 2005, which defines the set of instructions the chips can execute; verification software and simulation models to test software on chip designs; and a version of Solaris 10 that can be used in such simulations.
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