Accelerating AMD
Published: 04 Jan 2006 17:55 GMT
...building all the hardware infrastructure and the software infrastructure to support it, the idea here is that it's a lot less development expense and, in my opinion, a lot easier to leverage the standard software infrastructure that's there.
Is this a radical shift in AMD's strategy?
Yes and no. The nice thing about this is the AMD64 design is a reliable, high-volume cross-platform. The ecosystem is in place to support that already because it's fully compatible over the Linux and Microsoft software out there. It's also non-disruptive as you... move upstream. That is not the case with Itanium, for example.
I think AMD now is at the point that the base hardware level is very competitive, and the question for us now is, "Okay, you have a great platform; now what do you do?" And so my bias is, once you got a base platform, you want to effectively then build on that very quickly at all levels. There'll be elements of that or hardware-enabling technologies like a licence to coherent HyperTransport. There'll be work we'll do with Microsoft and the software Linux community to deal with things like ease-of-use or reliability features and recovery, and virtualisation partitioning. So to me, it's the next level of focus in the industry, beyond just the raw silicon level.
Let's talk about AMD's raw silicon level. Opteron and Athlon chip architectures are based on your K8 designs, previously called Hammer. Is there a K9 — or Hammer 2 — in the works?
There are two separate discussions related to that question. One is the software-visible instruction set architecture, the ISA. The second thing is the internal architecture of how you actually implement that in silicon, and so those two things are separable.
Let me give you some examples. If you look at what we're doing around virtualisation and security on Pacifica [which will let computers run multiple operating systems] and Presidio [a security technology that ensures separate processes can't interfere with each other], those were ISA extensions. Obviously, hardware changes are needed under the covers to implement that, but there are those who have done so largely around the microarchitecture code that exists today. So, AMD's kind of manufacturing in strategy is roughly every quarter we've got a higher performance transistor and so you kind of keep the same underlined microarchitecture and incrementally improve new manufacturing technology. So, the structure of the microarchitecture largely stays the same.
Then there is a brand new core design that has to be fully backwards compatible with the old instruction set architecture. Then you can also choose to introduce new instruction set extensions at the time of that new core. So, what you typically see is a core that lives — depending on the market segment — two to four years, and so then you want to time the introduction of a new core with major changes that you need at the system level.
At that point, you could look at things like next-generation memory technology. There'll be cases where you'd want to introduce a new generation core along with the new memory technology. There will be other cases where, for example — and that's the case right now that lot of people told us — they want to keep the same base design that we've got, but go to DDR2 as opposed to Intel's FB-DIMMs. So it's really kind of...
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