Will Intel smash the silicon barrier?
Published: 01 Mar 2005 17:10 GMT
In a wide-ranging briefing given the day before Tuesday's start of the Intel Developer Forum in San Francisco, Intel gave some details of the smorgasbord of techniques and innovations it claims will keep the rate of improvement of chips constant for the next fifteen to twenty years. Intel and the rest of the chip world lives by Moore’s Law, the prediction made forty years ago by Intel founder Gordon Moore that chips would double in function every two years. At some point, it is generally agreed that the laws of physics will have to eventually slow this down. By continual tweaking and the gradual introduction of nanotechnology, Intel said, this point can be pushed to 2020. However a phased switch to non-silicon logic could well see Moore’s Law continuing beyond the next fifteen years, the company claims.
The basic functional block of the chips that Intel makes is the CMOS transistor, a device that in cross-section looks somewhat like a cream éclair. Voltage applied to the cream allows current to flow across the cake. As the transistor shrinks, the speed at which the transistor can switch on and off increases -- however, it gets more difficult to make and other factors, such as leakage current (which flows whether it should or not) reduce the performance in different ways. In all, there are around 10 factors in transistor design that change with size.
In 1997, it was commonly assumed that once the 100nm limit was reached, CMOS would run out of steam on both performance and cost benefit grounds. However, each parameter is prone to individual tweaking once it approaches a problem area, and as the geometry of the transistor has been steadily shrunk the basic structure has proved very resilient.
For example, there’s an insulating layer that’s part of the standard transistor design. This was 8nm thick in 1992, and had reduced to 1.2nm by 2002 with 90nm architecture. The thinner the layer, the faster the transistor. However, it stayed at 1.2nm in 2004 with 65nm processes, for the simple reason that the layer was only four atoms thick. It couldn’t be any thinner and physically act as an insulator. Traditionally, this layer’s been made out of silicon dioxide: by replacing it with another material called a high-K dielectric, the layer can be physically thicker but act electrically as if it was much thinner. It also reduces the leakage current through the transistor, which contributes extensively to the power used by a chip. With high-K dielectrics, the insulating layer can continue to be refined, and performance increases expected, for at least another decade.
Another advantage comes from putting the basic silicon lattice in a transistor under strain. This rearranges the atoms in such a way that electrons can move through them more easily, increasing speed or reducing losses depending on which is more useful in a particular application. For processors which dynamically trade off speed for lower power consumption, this increases the range over which they can usefully operate.
The public roadmap for Intel’s core transistor design goes to 2011, where 22nm devices built on strained silicon with metal electrodes and high-K dielectrics. Intel has plenty of exotica up its sleeve for progress past this point: tri-gate transistors, where the control input of the device is no longer a simple layer on top but is wrapped around three sides of the transistor. This is more difficult to fabricate, but removes two potential leakage paths.
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