Intel: Montecito or bust?
Published: 09 Sep 2004 10:40 BST
Following Intel's first public demonstration of its latest Itanium -- the dual-core Montecito -- Abhi Talwalkar, general manager of Intel's Enterprise Platform Group, talked to ZDNet UK about future plans for the technology, how Itanium is currently being targeted and how the market for the chip will develop.
If you drop in a Montecito to a Madison-based system you claim around a 2x performance increase. Can we expect that sort of performance with each new generation of Itanium?
That's without recompilation -- you can get better than that if you recompile. For future performance increases, you have to look at Itanium history. From Merced to McKinley was a two times increase - that was an architectural change. From McKinley to Madison was 1.5x, a process shrink, but Madison to Montecito is an architectural change again with dual core and multi-threading and we're back to 2x.
It all depends on whether there's an architectural change or a process shrink. Montecito was a ground-up redesign to make it the best multi-core architecture. The cache size increase is another architectural change, but you'll see other changes beside that. There are good questions about what do you do if you have more than two cores -- what's the cache structure then? Montecito's cache is 24 megabytes (MB), it's really two independent caches of 12MBeach, fed by one bus interface. It's a pretty big bus.
How will Intel's lack of a chipset for larger servers affect the market?
We have our own chipset for two-way and four-way, but a lot of the development is greater than four-way and there the OEMs are developing their own chipsets. Most of these guys are RISC vendors, and they've been making investment in the RISC sides, and that's been more and more shipping over to Itanium2. NEC's a great example. NEC made a decision six or seven years ago to decrease investment on their proprietary microprocessors large scale systems and increase commensurately on It2. There'll be no white box activity above four-way Itanium2.
Won't that space be filled by Xeons?
There are 16 and, I think, 32 way Xeons in that space. Most of the scale-up work is in the Itanium2, because of our architectural advantages in the highly parallel EPIC architecture. We scale up a lot better, we have virtualisation that'll show up first in Montecito, a great technology for scaling up platforms. We have RAS advantages [reliability, availability and serviceability] in the silicon itself.
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