Intel shows off next-generation production tricks
Published: 24 Nov 2003 21:25 GMT
Intel has announced its first test production of four-megabit static memories using 65-nanometre technology. This marks a key stage in the company's preparation for 65nm products in 2005, two years after 90nm is due to enter full service. "This demonstrates the importance of being an integrated device manufacturer," said Mark Bohr, a senior fellow at Intel and director of process architecture and integration. "We control the silicon process, the mask making and the circuit design, and the increasingly complex interactions between them."
Key developments in the new process have included ways to create features with a greater precision than the wavelength of light used would normally allow, by compensating for the distortion. This means that existing equipment based on 192nm wavelength light can be used not only for 65nm technology but the next generation after that, 45nm, due in 2007. After that, said Bohr, new techniques using extreme ultraviolet would be needed. The 65nm process also used strained silicon, a method of improving the conductivity and reducing the power loss in chips that was first used in the 90nm production process behind Intel’s Prescott next-generation Pentium chip.
The memory cell demonstrated packs six transistors into half a square micrometre, a density equivalent to putting ten million transistors on the tip of a ballpoint pen. "This keeps us on track with Moore's Law," Bohr said, "and the introduction of a new technology every two years."
AMD and IBM are also working on 65nm technology, based on Silicon-On-Insulator (SOI) technology instead of Intel's strained silicon solution, although Intel claims that it expects to be the first company to market with the new size.
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