IBM conserves power with new chip
Published: 15 Oct 2003 08:40 BST
IBM's upcoming Power5 will include new features to curtail the chip's consumption of electrical current, the company said on Tuesday.
The Dynamic Power Management technology can execute "50 percent more instructions using same amount of energy, without any performance impact" compared to the current Power4+ chip, Power5 chief scientist Balaram Sinharoy said. The power management feature works both when the chip is hard at work and when it is waiting idle for new instructions, he said during a talk at the Microprocessor Forum here.
Power consumption, which is directly related to a chip's waste heat, is one of the major constraints on processor and computer design. Chips that run too hot can trigger system errors and crashes. In addition, it's expensive for hardware makers to design, and for customers to operate, cooling systems for computers and data centres filled with computing gear.
The Power processor family is the heart of IBM's sustained -- and so far, successful -- effort to gain ground in the Unix server market on No. 1 Sun Microsystems and No. 2 Hewlett-Packard. Unlike those rivals' Unix systems, however, IBM's Power line also runs two other operating systems, Linux and OS/400.
The Power5 is scheduled to arrive in servers in 2004, Sinharoy said, adding that a second-generation revamp called the Power5+, built using a more-advanced manufacturing process, is expected to launch in 2005. IBM plans to release the Power5 chip in a 64-processor server code-named Squadron.
Power5, like Power4, includes two processor cores in a single slice of silicon. That "dual-core" design has been pioneered by IBM, but rivals Sun Microsystems and Intel are following. Unlike Power4, though, each Power5 processor will be able to simultaneously execute two tasks, called "threads."
Through this combination of multithreading and dual-core technology, the Squadron computer loaded with a maximum 32 Power5 chips will appear to software to have 128 processors, Sinharoy said. That compares with Big Blue's current P690 "Regatta" system, which has 16 dual-core Power4 chips that function as a 32-processor server.
The simultaneous multithreading technology can be switched off to allow one of the two threads to operate at maximum speed, Sinharoy said. Otherwise, Power5 will monitor the priority of each thread to make sure one doesn't end up hogging all the resources. In addition, when the system is in a power-saving mode for moments of idleness, it will be able to assign both threads the lowest priority possible, so the system consumes as little power as possible.
Power5 will measure 389 square millimetres and contain 276m transistors, according to IBM. Groups of four Power5 chips will be packaged in a single "multichip module (MCM)," which is a square slab of ceramic and metal laced with thousands of internal wires that connect the chips. IBM drew the MCM packaging from its top-end mainframe server line.
In another difference from Power4, Power5 will have a memory controller built into the silicon instead of requiring a separate chip to govern communications with memory, Sinharoy said. That strategy -- which Sun has already taken with its current UltraSparc III processor and which Advanced Micro Devices has used with its Opteron -- will speed up memory access and improve system reliability, he said.
One thing that's the same in both Power4 and Power5 is the "pipeline," which is the series of processing steps a chip performs as it converts input data to a result. The Power4 and Power5 pipelines are identical, Sinharoy said, though other parts of the chip have been changed to accommodate the multithreading technology.
Power5 will also include new features to improve what's called "RAS" in tech industry circles: reliability, availability and serviceability. Specifically, the chip will be able to continue working during an upgrade of a computer's "firmware," which is a program similar to operating system software but that operates at a deeper level.
Power5 is also designed to protect more data pathways in the chip with error-correction code (ECC) and to automatically fix some data transmission errors.
On Tuesday, IBM also gave some hints about its Power6 chip, scheduled for delivery in 2006. Although the company didn't specify how many processor cores the Power6 would have, it did describe them as "ultra-high frequency." In addition, it said Power6 would be built using a manufacturing process in which chip features are 65 nanometres in length. (A nanometre is a billionth of a metre; newer manufacturing processes with smaller feature sizes permit more circuitry to be built onto chips.)
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