Intel 'peels onion' with nanosurgery
Published: 16 Sep 2003 11:15 BST
One final tuning process involves checking the circuit for abnormal power usage. The chip is run in test mode, while an ultra-sensitive IR imaging system produces a thermal map of the silicon. Any area that uses more power than the rest appears in stark relief: however, the system is so exquisitely sensitive that temperature differentials of 0.01 degrees Celsius can be detected. This shows up leakage currents flowing in chips in hibernation or suspension.
All these techniques are in use on Intel's 90nm architectures. Because of limitations due to the wavelength of IR light -- already a factor of ten larger than the components it investigates, and thus unsuited to pinpoint fine details -- another generation of test technologies is required for the 65nm chips coming up next. Intel isn't discussing those, nor how it proposes to test complex three-dimensional structures as found in advanced transistor geometries and nanotech devices. That it feels free to talk about the current test systems is an indication of their maturity -- something also shown by the way Intel uses them to produce batches of fixed chips to feed back into its verification process.
Other companies have similar processes: in fact, Silicon Valley works in part by chip companies working with test equipment makers to develop these new ideas and letting them sell the results to all comers. The original company gets patents and licence fees, first dibs on the equipment and a lead of a year or two in using the techniques, but new concepts are quickly shared out between companies who appear on the surface to be sworn enemies. In this, as much as in the basic physics, chip companies ensure a regular flow of all the technologies necessary to keep new developments coming out of the labs and onto the shelves.
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