Buses, bottlenecks and speed
James McPherson
Published: 24 Sep 2002 08:21 BST
A-Link
ATI's response to VIA's VLink is the A-Link. It too is a dedicated 266-MBps motherboard bus that connects the memory controller and CPU with the other peripherals. Like VLink, it has so far performed its job as expected, but A-Link will need some revision in the future to keep up with the proliferation of near-future devices.
FireWire 2/IEEE 1394b
FireWire has become a favorite for the digital video crew and users who need fast external storage due to its 400-Mbps of bandwidth and lengthy 4.5 m cables. FireWire 2 doubles the baseline speed up to 800 Mbps, and in proposed optional variations, can reach over 1 GBps for lengths of up to 100 meters using a variety of cabling. The new version is intended to compete with Fibre Channel and SCSI over IP in storage area networks (SANs) or as inexpensive short-hop gigabit networks. Desktop versions of FireWire 2 will be backwards-compatible with FireWire 1 and will advance the nonpowered iLink variant. Multiple wiring formats will be supported, ranging from CAT 5 to optical fiber. As of this writing, it is not yet clear whether the new version has been approved as an IEEE standard. The IEEE Web site states that a vote recommends accepting the standard, but there are no official notices of a final version on the FireWire site. If all goes well, we should see FireWire 2 devices on the market in the next six months.
The memory factor
As processor clock speed increases, memory speed has become the main limitation on computer performance. I'll examine some of the newer memory technologies and how they affect bus development.
DDR II
DDR, or as it will soon be known, DDR I, provided a cost-effective way to increase bandwidth over SDRAM. DDR is currently available at speeds up to 333 MHz. 400 MHz DDR I is in development, but it involves such precise tolerances that it is not expected to be cost-effective.
DDR II will be a revamped implementation of DDR based on a smaller 0.13-micron process. Basic operating commands will be the same, but DDR II will have double-size data prefetch, multiple burst lengths, and read/write latency settings. Also, memory latency will no longer include half-cycle latencies, which will simplify timing issues. PC versions of DDR II will initially be available at 400 MHz (3.2 GBps), with 533 MHz (4.3 GBps) and 667 MHz (5.4 GBps) to follow. Higher-speed DDR II for video and switching devices will be available at speeds of up to 1 GHz.
DDR II is expected to provide a noticeable boost to performance, even at the same bandwidth. So far, asynchronous memory and processor front-side bus speeds have proven to be troublesome. 533 MHz DDR II has no more bandwidth than dual-channel 266 MHz DDR I but should be far more efficient on the new Pentium 4's 533-MHz interface than the current 333-MHz DDR I. It is uncertain how long it will be before DDR II will reach the market. However, DDR II will be necessary in the next year to keep from bottlenecking the processors that will be available by then.
RDRAM
Current-generation RDRAM operates at speeds of 800 MHz (1.6 GBps). The upcoming increment of RDRAM operates at 1066 MHz to provide 4.2 GBps in a fixed dual-channel configuration (2x 2.1 GBps). The 1066-MHz speed will provide a synchronous connection to the 533-MHz Pentium 4 front-side bus, which is far superior to using the 800-MHz variant. How well it will compare to 533-MHz DDR II will be of great interest, because DDR II will require fewer components and have better latency. RDRAM's advantage is that 1066 MHz will be reaching the market soon, with 1200 MHz (2.4 GBps per channel) on the far horizon.
Rambus II
While Rambus II is not the exact moniker of the new Yellowstone technology to be introduced by Rambus, it will do for our purposes here. Yellowstone is a technique for increasing the clock speed of RDRAM. Rather than the normal double data rate format of two transfers per clock of current RDRAM and DDR, Rambus II will use octal data rates (ODR) of eight transfers per clock. This allows an effective 3.2 GHz from a mere 400-MHz clock. Yellowstone will scale to an effective 6.4 GHz. It is intended to use a mere 1-byte data path, but at these speeds, this will provide an initial 3.2 GBps per channel, far superior to current RDRAM, with final speeds of 6.4 GBps per channel.
High bandwidth will be welcome, but latency may be a problem. Cost will also be a concern for this new technology, as an octal clock will require severe tolerances. While manufacturing will be a bit easier (given the slower core clock), the intended low voltages will make sensing the minute shifts required for an octal clock difficult. Only time will tell how well Rambus II will perform in the market.
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