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Buses, bottlenecks and speed

James McPherson Tech Republic

Published: 24 Sep 2002 08:21 BST

A new device can increase its data transfer speed only so much before it becomes bottlenecked by the bus interface. Some devices are phased out slowly, like ESDI hard drives; others come and go in a flash, much like the VL Bus. Regardless of the time frame, as these devices reach obsolescence, new bus standards are currently under development (or are already developed) to keep pace with this increase in bandwidth.

Bus overview
A bus allows multiple devices to communicate, as compared to an interface, which is the connection from one device to another device or bus. Most buses include a standardised set of interfaces you can use to attach devices to the bus. There may be multiple interfaces to a given bus, however, reflecting various performance levels or generations. For example, the soon-to-be-obsolete EISA bus supports either the short 16-bit interface or the longer 32-bit interface.

A bus's performance and capabilities can be measured by these four features: data width, cycle rate, device management, and type. The data width and cycle rate are used to determine the bandwidth, or the total amount of data that the bus can transmit. For example, an 8-bit bus (1-byte data width) that operates at a cycle rate of 1,000 MHz (1,000,000 times per second) can transfer 8 Mbps (1 MBps).

The device-management specification indicates the maximum number of supported devices, how they connect, and the difficulty of configuring them. There are two types of bus communications: serial and parallel. On a parallel bus, all devices have their own interface to the bus, which until recently was the norm. Serial devices are tied together in a series; the last one has to talk "through" the first one. This can obviously cause performance problems, but it allows more devices to be connected to the system up to the limit of serial addresses available.

Serial ATA
The darling of Intel, Serial ATA is the company's response to Apple's FireWire (IEEE 1394) and its intended replacement for parallel ATA, which is the interface used by EIDE devices. Serial ATA is a serial bus that daisy-chains drives together in a way that is software-compatible with the current ATA standard. Despite being a serial interface, it is designed to provide two point-to-point connections, one for each drive, eliminating the master/slave issue. Furthermore, it uses the same connector for both full-size drives and floppy drives, removing another point of confusion.

First-generation Serial ATA, which may be available later this year, provides 150 MBps of bandwidth per drive. Second-generation Serial ATA (Serial ATA II) will allow up to 300 MBps of bandwidth and will be backwards-compatible with Serial ATA I. Contrast this to the 100 MBps per controller of ATA/100 and the not-yet-standardised 133 MBps of ATA/133, and you can see how little impact first-generation Serial ATA will have. Admittedly, Serial ATA will enable both drives on a chain to operate simultaneously, and effectively double the bandwidth. However, the current limit of the ATA bus is due to the fewer drives per controller and the speed of IDE hard drives. This inherent address limitation, along with Serial ATA's one-meter total cable length, implies that this solution is more of an incremental upgrade.

Nonetheless, Serial ATA controllers will be cheaper than SCSI controllers, and the smaller cables are intended to be easier to use than Parallel ATA, while allowing more airflow in the case. However, until ATA hard drives match the performance and durability of SCSI drives, Serial ATA will remain a desktop technology not much different from Parallel ATA.

HyperTransport
This new bus standard from AMD was pioneered to replace the EV6 bus on motherboards. Since that time, it has been adopted by a number of companies for a variety of roles. At its core, HyperTransport is a scalable and variable-bandwidth bus using prioritised data packets. Most buses are designed with a time-slicing technique for sharing bandwidth. So, if you have a 100-Mb Ethernet card and a 56K modem on the same bus, the Ethernet card will get the full bandwidth for more time, and any lag is covered by data caches. Other buses use master/slave configurations in which multiple groups of devices can communicate, but the master can supercede the slave within their pairing, and no one device can use the full bandwidth of the bus.

HyperTransport contrasts this master/slave configuration with the ability for any device to use the full bandwidth available or multiple devices to use various fractions of the total bandwidth. This ability can be reassigned dynamically based on a priority system, ensuring key components receive the bandwidth they need.

HyperTransport does not have a specified bandwidth because the data width can be varied at manufacture. Thus, HyperTransport is a high-level bus that will typically connect other buses or systems. Motherboard manufacturers see great advantage in HyperTransport because it removes the PCI bus as the primary link for the IO system in a cost-effective manner. Expect to see HyperTransport appearing in a variety of multi-IO devices. This should help decrease the cost of PDAs, PCs, and laptops as the industry standardises on HyperTransport.

VLink
Developed by VIA Technologies, the VLink is a dedicated 266-MBps motherboard bus that connects the memory controller and CPU with the other peripherals. This fixed-configuration bus competes with HyperTransport on the motherboard. Only available with VIA chipsets, it is an in-house solution to the bandwidth problems motherboards face. While VLink has performed admirably in its chosen role, it will likely require revision in the coming months as more and more high-bandwidth devices become standardised.