New IBM technology to boost chip speed
Published: 03 Dec 2001 09:53 GMT
IBM will describe a new type of transistor this week that it says will vastly increase the performance and reduce the power consumption of chips in the coming decade.
In a presentation at the International Electron Devices meeting that starts Monday in Washington, DC, Big Blue will show off what it calls a Double Gate transistor. Transistors, which are microscopic on-off switches inside semiconductors, channel electronic signals that eventually get orchestrated into higher commands.
Double Gate transistors improve on existing designs, according to IBM, because they effectively double the electrical current that can be switched for a given signal, or, alternatively, lower the amount of electricity running through a given gate for better power management. Although multiple gate architectures have been used for many years in transistor design, IBM has combined the idea with more recent advances to make a device with great potential for logic systems.
"These are suited for very high-performance (processors) or for very low power," said Bijan Davari, vice president of semiconductor development at IBM Microelectronics. IBM has already made samples of Double Gate transistors, he added, which will likely start to appear in chips by 2006.
IBM's presentation underscores two of the major trends in the semiconductor world:
"Because the industry is going through one of these bends in the road, if you don't use (new power management technologies), you will be left behind," Davari said.
In the early 1990s, IBM would often release its advances to the industry somewhat liberally. Now, the company is getting "a lot more rigorous" about how it licenses technological developments and about how they come to market, Davari noted. "Technological leadership is a critical cornerstone of our business."
The competition of ideas is sprouting up all over. At the same conference this week, Intel will be presenting a paper--though no samples--on its "Terahertz" transistor architecture, which Intel says will cut power and improve performance in the next decade's chips.
IBM is also competing with Hewlett-Packard over nanotechnology, including proposed methods for building chips out of self-aligning strands of carbon molecules. Although IBM asserts that nanotechnology may not hit the market in a significant way for another 20 years, HP researchers believe elements of it will reach commercial production within five to 10 years in hybrid silicon-nano chips, said Stan Williams, an HP fellow.
The Moore the merrier?
The processor space race largely comes as a function of Moore's Law. Under Moore's Law, the number of transistors on a chip doubles roughly every 18 to 24 months through, among other factors, shrinking the transistors. The transistor explosion has allowed computers to experience continual improvements in performance.
But smaller, faster transistors in greater numbers mean that chips need more electricity, which creates a host of problems. Synchronising ever faster pulses across more complex circuits makes huge demands on design skills.
At the same time, faster signals in greater numbers can lead to signal interference. In addition, more energy means more heat. Without any structural changes, for instance, future power-hungry chips will be hotter than an equivalent slice of the sun's surface.
"Physics was once our friend," said Nathan Brookwood, an analyst at Insight 64. "Now it is our enemy."
With Double Gate, IBM is fiddling with the basic structural elements of transistors.
Transistors generally consist of three basic elements: a source, a gate and a drain. The gate normally sits on top of the connection between source and drain, much like a thumb on top of a hosepipe. Changing the voltage on the gate changes the resistance between source and drain, in effect pressing down or letting up on the hosepipe.
This can be used to change logic states in circuits between zero and one -- the true and false at the heart of computing. In Double Gate transistors, the gate, rather than merely sitting on top of the source and drain, wraps around the source-drain connection like a clamp -- the same voltage thus exerts greater change, resulting in a more efficient system.
IBM is also using silicon-on-insulator (SOI) in this architecture, which introduces a thin layer of insulating material to the side of the transistor, keeping charge effects in the substrate of the chip well away from the active, switching area. SOI is one of the crucial elements of the new design, Davari said. A form of SOI is also critical to Intel's upcoming "Terahertz" transistor, which Davari finds ironic because Intel has criticised it for years.
"They've been bashing it at all the technical conferences," Davari said. IBM has promoted SOI since 1998 and incorporated the technology in several chips. Although Intel executives admit that the company has criticised SOI, researchers there claim that their version of SOI, due out toward 2005, is better.
IBM will use Double Gate transistors in its own chips and license it to its foundry clients, Davari said.
ZDNet UK's Rupert Goodwins contributed to this report.
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